As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, there have been challenges in controlling flatness of an underlying layer in view of lithography operations. A flash memory utilizing non-volatile memory (NVM) cells has continually been scaled down and is embedded in advanced CMOS logic integrated circuits (ICs) for a smart card and automotive applications. In particular, integration of manufacturing processes for the NVM cells and manufacturing processes for peripheral logic circuits become more complex and important.